所属类别：工人/技工/普工

所在城市：北京

发布日期：20080916 17:31:32

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Requirements: 5 years of hands on experience on high speed digital RTL design using verilog. Experience on developing simulation testbench. Experience on DC compiler synthesis tools. Experience on prime time static timing tools. Completed at least one million gate chip design projects from architectural phase to tape out. Wireless and communication system experience is a plus.

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